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Silicon Labs /Series0 /EZR32HG /EZR32HG320F64R63 /TIMER0 /IEN

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Interpret as IEN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OF)OF 0 (UF)UF 0 (CC0)CC0 0 (CC1)CC1 0 (CC2)CC2 0 (ICBOF0)ICBOF0 0 (ICBOF1)ICBOF1 0 (ICBOF2)ICBOF2

Description

Interrupt Enable Register

Fields

OF

Overflow Interrupt Enable
UF

Underflow Interrupt Enable
CC0

CC Channel 0 Interrupt Enable
CC1

CC Channel 1 Interrupt Enable
CC2

CC Channel 2 Interrupt Enable
ICBOF0

CC Channel 0 Input Capture Buffer Overflow Interrupt Enable
ICBOF1

CC Channel 1 Input Capture Buffer Overflow Interrupt Enable
ICBOF2

CC Channel 2 Input Capture Buffer Overflow Interrupt Enable

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data